High performance OTP based 8bits RISC architecture core.
?Compatible with YSM14x/34x 50 instructions.
?16-bit wide instruction with 8-bit wide data path.
?2K x 16bits OTP ROM.
?160 x 8bits general purpose RAM with direct and indirect access.
?16 levels hardware stack(Occupy at highest 32bytes in GPR).
?Flexible function configuration.
?2 steps Core Speed(Internal RC mode).
?Up to 10MIPS operation

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